1. Field of the Invention
The present invention relates to a transistor and a method of manufacturing the transistor. More particularly, the present invention relates to a highly integrated transistor that includes improved impurity regions, and a method of manufacturing the transistor.
2. Description of the Related Arts
In general, a transistor of a semiconductor device includes a gate structure formed on a semiconductor substrate, and source/drain regions provided at portions of the substrate adjacent to both sides of the gate structure. The gate structure includes a gate insulation layer pattern formed on the substrate, a conductive layer pattern formed on the gate insulation layer pattern, a hard mask layer pattern formed on the conductive layer pattern, and spacers formed on sidewalls of the conductive layer pattern.
The conductive layer pattern selectively forms a channel region in the substrate, which electrically connects the source region to the drain region. The source region provides carriers to the channel region, whereas the drain region discharges the carriers provided from the source region.
In the conventional transistor, an interface between the source/drain regions and the substrate may be damaged due to a hot carrier effect caused by rapid electrons. To prevent the hot carrier effect, there is provided a method of forming source/drain regions having lightly doped drain (LDD) structures. However, in a process for forming the LDD structures, impurities may diffuse into the substrate to thereby reduce a width of the channel region while the impurities are thermally treated to form the source/drain regions. As a semiconductor device has been highly integrated, the width of the channel region has been additionally reduced. This is referred to as a short channel effect. When the width of the channel region is reduced, a depletion layer adjacent to the source region may be electrically connected to a depletion layer adjacent to the drain region so that punch-through may occur in the transistor. Punch-through is a phenomenon in which the carriers move between the source region and the drain region through the channel region although a threshold voltage is not applied to the conductive layer pattern. When punch-through occurs in the transistor, the transistor may fail completely.
To prevent the short channel effect in the LDD structures, a method of forming a semiconductor device having a single drain cell structure is disclosed in U.S. Pat. No. 6,599,803 and U.S. Pat. No. 6,605,498. According to the method disclosed in the above U.S. Patents, recesses are formed at both sides of a gate electrode. Epitaxial layers including silicon-germanium grow in the recesses to form the single drain cell structure. In addition, a method of forming a semiconductor device is disclosed in Korean Patent Laid Open Publication No. 2003-82820. According to the method disclosed in the above Korean Patent Laid Open Publication, trenches are formed at both sides of a gate electrode. Spacers including insulating material are formed in the trenches under sidewalls of the gate electrode.
The above-mentioned conventional methods of forming a transistor having the single drain cell structure may have some advantages such as a relatively low resistance, a steep PN junction, a reduced thermal budget, etc. Thus, the conventional methods of forming a transistor may be employed for a transistor having a gate width of below about 100 nm.
However, the transistor formed by the conventional methods still has characteristics that can be improved upon, such as a lower resistance, more steep PN junctions, etc. Therefore, the conventional method may not be easily employed for a highly integrated transistor having a gate width of below about 10 nm.